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CY14E256LA
256-Kbit (32 K x 8) Nonvolatile SRAM
256-Kbit (32 K x 8) Nonvolatile SRAM
Features

Functional Description
The Cypress CY14E256LA is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 32 KB. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world's most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.
25 ns and 45 ns access times Internally organized as 32 K x 8 (CY14E256LA) Hands-off automatic STORE on power-down with only a small capacitor STORE to QuantumTrap nonvolatile elements initiated by software, device pin, or autostore on power-down RECALL to SRAM initiated by software or power-up Infinite read, write, and RECALL cycles 1 million STORE cycles to QuantumTrap 20-year data retention Single 5 V +10% operation Industrial temperature 44-pin thin small-outline package (TSOP II) and 32-pin small-outline integrated circuit (SOIC) package Pb-free and restriction of hazardous substances (RoHS) compliant
Logic Block Diagram
Cypress Semiconductor Corporation Document Number: 001-54952 Rev. *F
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 17, 2011
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CY14E256LA
Contents
Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Device Operation .............................................................. 4 SRAM Read ....................................................................... 4 SRAM Write ....................................................................... 4 AutoStore Operation ........................................................ 4 Hardware STORE Operation ............................................ 4 Hardware RECALL (Power-up) ........................................ 5 Software STORE ............................................................... 5 Software RECALL ............................................................. 5 Preventing AutoStore ....................................................... 6 Data Protection ................................................................. 6 Noise Considerations ....................................................... 6 Best Practices ................................................................... 7 Maximum Ratings ............................................................. 8 Operating Range ............................................................... 8 DC Electrical Characteristics .......................................... 8 Data Retention and Endurance ....................................... 9 Capacitance ...................................................................... 9 Thermal Resistance .......................................................... 9 AC Test Conditions .......................................................... 9 AC Switching Characteristics ....................................... 10 SRAM Read Cycle .................................................... 10 SRAM Write Cycle ..................................................... 10 AutoStore/Power-up RECALL ....................................... 12 Software Controlled STORE/RECALL Cycle ................ 13 Hardware STORE Cycle ................................................. 14 Truth Table For SRAM Operations ................................ 15 Ordering Information ...................................................... 15 Ordering Code Definition ........................................... 15 Package Diagrams .......................................................... 16 Acronyms ........................................................................ 17 Acronyms Used ......................................................... 17 Document Conventions ................................................. 17 Units of Measure ....................................................... 17 Document History Page ................................................. 18 Sales, Solutions, and Legal Information ...................... 19 Worldwide Sales and Design Support ....................... 19 Products .................................................................... 19 PSoC Solutions ......................................................... 19
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CY14E256LA
Pinouts
Figure 1. Pin Diagram - 44-Pin TSOP II / 32-Pin SOIC
NC [5] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 VCC VSS DQ2 DQ3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 HSB NC [4] NC [3] NC [2] NC NC [1] [1] NC OE DQ7 DQ6 VSS VCC DQ5 DQ4 VCAP A14 A13 A12 A11 A10 NC NC
44 - TSOP II
(x8)
32 - SOIC
(x8)
Top View (not to scale)
Top View (not to scale)
Pin Definitions
Pin Name A0 - A14 WE CE OE VSS VCC HSB I/O Type Input Input Input Input Ground Power supply Description Address inputs. Used to select one of the 32,768 bytes of the nvSRAM. Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. I/O pins are tri-stated on deasserting OE HIGH. Ground for the device. Must be connected to the ground of the system. Power supply inputs to the device.
DQ0 - DQ7 Input/Output Bidirectional data I/O Lines. Used as input or output lines depending on operation.
Input/Output Hardware STORE Busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress. When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection is optional). Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements.
VCAP NC
No connect No connect. This pin is not connected to the die.
Notes 1. Address expansion for 1 Mbit. NC pin not connected to die. 2. Address expansion for 2 Mbit. NC pin not connected to die. 3. Address expansion for 4 Mbit. NC pin not connected to die. 4. Address expansion for 8 Mbit. NC pin not connected to die. 5. Address expansion for 16 Mbit. NC pin not connected to die.
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CY14E256LA
Device Operation
The CY14E256LA nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations, SRAM read and write operations are inhibited. The CY14E256LA supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 1 million STORE operations. Refer to the Truth Table For SRAM Operations on page 15 for a complete description of read and write modes.
Note If the capacitor is not connected to VCAP pin, AutoStore must be disabled using the soft sequence specified in Preventing AutoStore on page 6. In case AutoStore is enabled without a capacitor on VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the Store. This corrupts the data stored in nvSRAM. Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic STORE operation. Refer to DC Electrical Characteristics on page 8 for the size of VCAP. The voltage on the VCAP pin is driven to VCC by a regulator on the chip. Place a pull-up on WE to hold it inactive during power-up. This pull-up is only effective if the WE signal is tristate during power-up. Many MPUs tristate their controls on power-up. This must be verified when using the pull-up. When the nvSRAM comes out of power-on-RECALL, the MPU must be active or the WE held inactive until the MPU comes out of reset. To reduce unnecessary nonvolatile stores, AutoStore and Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. Figure 2. AutoStore Mode
VCC
SRAM Read
The CY14E256LA performs a read cycle when CE and OE are LOW and WE and HSB are HIGH. The address specified on pins A0-14 determines which of the 32,768 data bytes each are accessed. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle 1). If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
10 kOhm
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DQ0-7 are written into the memory if the data is valid tSD before the end of a WE-controlled write or before the end of a CE-controlled write. Keep OE HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.
0.1 uF VCC
WE
VCAP VCAP
VSS
AutoStore Operation
The CY14E256LA stores data to the nvSRAM using one of the following three storage operations: Hardware STORE activated by HSB; Software STORE activated by an address sequence; AutoStore on device power-down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14E256LA. During a normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor.
Hardware STORE Operation
The CY14E256LA provides the HSB pin to control and acknowledge the STORE operations. Use the HSB pin to request a Hardware STORE cycle. When the HSB pin is driven LOW, the CY14E256LA conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver (internal 100 k weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by internal 100 k pull-up resistor.
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CY14E256LA
SRAM write operations that are in progress when HSB is driven LOW by any means are given time (tDELAY) to complete before the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. In case the write latch is not set, HSB is not driven LOW by the CY14E256LA. But any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or other external source. During any STORE operation, regardless of how it is initiated, the CY14E256LA continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. Leave the HSB unconnected if it is not used.
To initiate the Software STORE cycle, the following read sequence must be performed: 1. Read address 0x0E38 Valid READ 2. Read address 0x31C7 Valid READ 3. Read address 0x03E0 Valid READ 4. Read address 0x3C1F Valid READ 5. Read address 0x303F Valid READ 6. Read address 0x0FC0 Initiate STORE cycle The software sequence may be clocked with CE controlled reads or OE controlled reads, with WE kept HIGH for all the six READ sequences. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation.
Hardware RECALL (Power-up)
During power-up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, HSB is driven low by the HSB driver.
Software RECALL
Data is transferred from nonvolatile memory to the SRAM by a software address sequence. A Software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation. To initiate the RECALL cycle, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x0E38 Valid READ 2. Read address 0x31C7 Valid READ 3. Read address 0x03E0 Valid READ 4. Read address 0x3C1F Valid READ 5. Read address 0x303F Valid READ 6. Read address 0x0C63 Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared. Next, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements.
Software STORE
Data is transferred from SRAM to the nonvolatile memory by a software address sequence. The CY14E256LA Software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place.
Table 1. Mode Selection CE H L L L WE X H L H OE X L X L A14 - A0[6] X X X 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0B45 Mode Not selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore disable I/O Output high Z Output data Input data Output data Output data Output data Output data Output data Output data Power Standby Active Active Active[7]
Notes 6. While there are 15 address lines on the CY14E256LA, only the lower 14 are used to control software modes. 7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
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CY14E256LA
Table 1. Mode Selection (continued) CE L WE H OE L A14 - A0[6] 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0B46 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0FC0 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0C63 Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL I/O Output data Output data Output data Output data Output data Output data Output data Output data Output data Output data Output data Output high Z Output data Output data Output data Output data Output data Output high Z Power Active[7]
L
H
L
Active ICC2[7]
L
H
L
Active[7]
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x0E38 Valid READ 2. Read address 0x31C7 Valid READ 3. Read address 0x03E0 Valid READ 4. Read address 0x3C1F Valid READ 5. Read address 0x303F Valid READ 6. Read address 0x0B45 AutoStore Disable The AutoStore is reenabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the Software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x0E38 Valid READ 2. Read address 0x31C7 Valid READ 3. Read address 0x03E0 Valid READ 4. Read address 0x3C1F Valid READ 5. Read address 0x303F Valid READ 6. Read address 0x0B46 AutoStore Enable
If the AutoStore function is disabled or reenabled, a manual STORE operation (Hardware or Software) must be issued to save the AutoStore state through subsequent power-down cycles. The part comes from the factory with AutoStore enabled.
Data Protection
The CY14E256LA protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC is less than VSWITCH. If the CY14E256LA is in a write mode (both CE and WE are LOW) at power-up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power-up or brown out conditions.
Noise Considerations
Refer to CY application note AN1064.
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CY14E256LA
Best Practices
nvSRAM products have been used effectively for over 27 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices:

The nonvolatile cells in this nvSRAM product are delivered from Cypress with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer's sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product's firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
Power-up boot firmware routines should rewrite the nvSRAM into the desired state (for example, AutoStore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. The VCAP value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum VCAP value because the nvSRAM internal algorithm calculates VCAP charge and discharge time based on this maximum VCAP value. Customers that want to use a larger VCAP value to make sure there is extra store charge and store time should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period.
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CY14E256LA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................-65 C to +150 C Maximum accumulated storage time: At 150 C ambient temperature........................ 1000 h At 85 C ambient temperature...................... 20 Years Ambient temperature with power applied..-55 C to +150 C Supply voltage on VCC relative to VSS ........... -0.5 V to 7.0 V Voltage applied to outputs in high Z state ..........................-0.5 V to VCC + 0.5 V Input voltage........................................... -0.5 V to Vcc+0.5 V Transient voltage (<20 ns) on any pin to ground potential.................. -2.0 V to VCC + 2.0 V Package power dissipation capability (TA = 25 C)...................................................1.0 W Surface mount Pb soldering temperature (3 seconds) ...........................................+260 C DC output current (1 output at a time, 1 s duration).....15 mA Static discharge voltage ......................................... > 2001 V (per MIL-STD-883, Method 3015) Latch up current .................................................... > 200 mA
Operating Range
Range Industrial Ambient Temperature -40 C to +85 C VCC 4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range (VCC = 4.5 V to 5.5 V) Parameter VCC ICC1 ICC2 ICC3 ICC4 ISB IIX[9] Description Power supply Average VCC current Average VCC current during STORE tRC = 25 ns tRC = 45 ns Values obtained without output loads (IOUT = 0 mA) All inputs don't care, VCC = Max Average current for duration tSTORE Test Conditions Min 4.5 - Typ[8] 5.0 - Max 5.5 70 52 10 - Unit V mA mA mA mA
- -
- 35
Average VCC current at All inputs cycling at CMOS levels. Values obtained without output loads (IOUT = 0 mA). tRC= 200 ns, VCC (Typ), 25 C Average VCAP current All inputs don't care. Average current for duration tSTORE during AutoStore cycle VCC standby current Input leakage current (except HSB) Input leakage current (for HSB) CE > (VCC - 0.2 V). VIN < 0.2 V or > (VCC - 0.2 V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. VCC = Max, VSS < VIN < VCC VCC = Max, VSS < VIN < VCC VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or WE < VIL
- -
- -
8 8
mA mA
-1 -100 -1 2.0 VSS - 0.5
- - - - - - - 68
+1 +1 +1 VCC + 0.5 0.8 - 0.4 180
A A A V V V V F
IOZ VIH VIL VOH VOL VCAP
Off-state output leakage current Input HIGH voltage Input LOW voltage Output HIGH voltage Output LOW voltage Storage capacitor
IOUT = -2 mA IOUT = 4 mA Between VCAP pin and VSS, 6 V rated
2.4 - 61
Notes 8. Typical values are at 25 C, VCC= VCC (Typ). Not 100% tested. 9. The HSB pin has IOUT = -2 uA for VOH of 2.4 V when both active high and low drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested.
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Data Retention and Endurance
Parameter DATAR NVC Data retention Nonvolatile STORE operations Description Min 20 1,000 Unit Years K
Capacitance
Parameter[10] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC (Typ) Max 7 7 Unit pF pF
Thermal Resistance
Parameter[10] Description Thermal resistance (Junction to ambient) Thermal resistance (Junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 44-TSOP II 32-SOIC 41.74 11.90 41.55 24.43 Unit C/W C/W
JA JC
Figure 3. AC Test Loads
5.0 V OUTPUT 30 pF
963 R1 R2 512
5.0 V OUTPUT 5 pF
963 R1
for tri-state specs
R2 512
AC Test Conditions
Input Pulse Levels ..................................................0 V to 3 V Input Rise and Fall Times (10% to 90%) ...................... <3 ns Input and Output Timing Reference Levels ................... 1.5 V
Note 10. These parameters are guaranteed by design and are not tested.
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AC Switching Characteristics
Parameters Cypress Alt Parameter Parameter 25 ns Description Min - 25 - - 3 3 - 0 - 0 - 25 20 20 10 0 20 0 0 - 3 Max 25 - 25 12 - - 10 - 10 - 25 - - - - - - - - 10 - Min - 45 - - 3 3 - 0 - 0 - 45 30 30 15 0 30 0 0 - 3 45 ns Max 45 - 45 20 - - 15 - 15 - 45 - - - - - - - - 15 - Unit
SRAM Read Cycle
tACE tRC[11] tAA[12] tDOE tOHA[12] tLZCE[13, 14] tHZCE[13, 14] tLZOE[13, 14] tHZOE[13, 14] tPU[13] tPD[13] tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE[13, 14,15] tLZWE[13, 14] tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Chip enable access time Read cycle time Address access time Output enable to data valid Output hold after address change Chip enable to output active Chip disable to output inactive Output enable to output active Output disable to output inactive Chip enable to power active Chip disable to power standby Write cycle time Write pulse width Chip enable to end of write Data setup to end of write Data hold after end of write Address setup to end of write Address setup to start of write Address hold after end of write Write enable to output disable Output active after end of write ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SRAM Write Cycle
Switching Waveforms
Figure 4. SRAM Read Cycle #1: Address Controlled [11, 12, 16]
tRC Address Address Valid tAA Data Output Previous Data Valid tOHA Output Data Valid
Notes 11. WE must be HIGH during SRAM read cycles. 12. Device is continuously selected with CE and OE LOW. 13. These parameters are guaranteed by design and are not tested. 14. Measured 200 mV from steady state output voltage. 15. If WE is low when CE goes low, the outputs remain in the high impedance state. 16. HSB must remain HIGH during READ and WRITE cycles.
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Figure 5. SRAM Read Cycle #2: CE and OE Controlled[17, 18]
Address Address Valid tRC tACE CE tAA tLZCE OE tLZOE Data Output High Impedance tPU Standby Active Output Data Valid tPD tDOE tHZOE tHZCE
ICC
Figure 6. SRAM Write Cycle #1: WE Controlled[18, 19, 20]
tWC Address Address Valid tSCE CE tAW tPWE WE tSA tSD Data Input tHZWE Data Output Previous Data tHD Input Data Valid tLZWE High Impedance tHA
Figure 7. SRAM Write Cycle #2: CE Controlled[18, 19, 20]
tWC Address tSA CE tPWE WE tSD Data Input Data Output Input Data Valid High Impedance tHD Address Valid tSCE tHA
Note 17. WE must be HIGH during SRAM read cycles. 18. HSB must remain HIGH during READ and WRITE cycles. 19. If WE is low when CE goes low, the outputs remain in the high impedance state. 20. CE or WE must be > VIH during address transitions.
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AutoStore/Power-up RECALL
Parameter tHRECALL[21] tSTORE[22] tDELAY[23] VSWITCH tVCCRISE
[24]
Description Power-up RECALL duration STORE cycle duration Time allowed to complete SRAM write cycle Low voltage trigger level VCC rise time HSB output disable voltage HSB to output active time HSB high active time
CY14E256LA Min Max - 20 - - - 150 - - - 8 25 4.4 - 1.9 5 500
Unit ms ms ns V s V s ns
VHDIS[24] tLZHSB[24] tHHHD[24]
Switching Waveforms
Figure 8. AutoStore or Power-up RECALL[25]
VCC VSWITCH VHDIS
22
t VCCRISE Note26 HSB OUT
tHHHD
Note
tSTORE tHHHD
Note 22
tSTORE Note
26
tDELAY tLZHSB tDELAY tLZHSB
AutoStore
POWERUP RECALL Read & Write Inhibited (RWI)
tHRECALL
tHRECALL
POWER-UP RECALL
Read & Write
BROWN OUT AutoStore
POWER-UP RECALL
Read & Write
POWER DOWN AutoStore
Notes 21. tHRECALL starts from the time VCC rises above VSWITCH. 22. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. 23. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY. 24. These parameters are guaranteed by design and are not tested. 25. Read and Write cycles are ignored during STORE, RECALL, and while VCC is less than VSWITCH. 26. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
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Software Controlled STORE/RECALL Cycle
Parameter[27, 28] tRC tSA tCW tHA tRECALL Description STORE/RECALL initiation cycle time Address setup time Clock pulse width Address hold time RECALL duration 25 ns Min 25 0 20 0 - Max - - - - 200 Min 45 0 30 0 - 45 ns Max - - - - 200 Unit ns ns ns ns s
Switching Waveforms
Figure 9. CE and OE Controlled Software STORE/RECALL Cycle[28]
tRC Address tSA CE tSA OE tHHHD HSB (STORE only) DQ (DATA) tLZCE tHZCE t DELAY Note
29
tRC Address #6 tCW tHA tHA
Address #1 tCW
tHA tHA
tLZHSB High Impedance tSTORE/tRECALL
RWI
Figure 10. AutoStore Enable / Disable Cycle
tRC Address tSA CE tSA Address #1 tCW tHA tHA tRC Address #6 tCW
tHA tHA
OE tLZCE DQ (DATA) tHZCE tSS
29
Note
t DELAY
Notes 27. The software sequence is clocked with CE controlled or OE controlled reads. 28. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles. 29. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.
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Hardware STORE Cycle
Parameter tDHSB tPHSB tSS
[30, 31]
Description HSB to output active time when write latch not set Hardware STORE pulse width Soft sequence processing time
CY14E256LA Min - 15 - Max 25 - 100
Unit ns ns s
Switching Waveforms
Figure 11. Hardware STORE Cycle[32]
Write Latch set
HSB (IN) tDELAY HSB (OUT) SO RWI tSTORE
~ ~
tPHSB
tHHHD
~ ~ ~ ~
tLZHSB
Write Latch not set
HSB (IN)
~ ~
tPHSB
HSB pin is driven high to VCCQ only by Internal 100 K resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven LOW. tDHSB
HSB (OUT)
tDELAY
tDHSB
RWI
Figure 12. Soft Sequence Processing[30, 31]
Soft Sequence Command Address Address #1 tSA Address #6 tCW tSS Soft Sequence Command Address #1 Address #6 tCW tSS
CE VCC
Notes 30. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command. 31. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. 32. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
Document Number: 001-54952 Rev. *F
~ ~
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CY14E256LA
Truth Table For SRAM Operations
HSB must remain HIGH for SRAM operations. Table 2. Truth Table CE H L L L WE X H H L OE X L H X High Z Data out (DQ0-DQ7) High Z Data in (DQ0-DQ7) Inputs/Outputs Read Output disabled Write Mode Deselect/power-down Standby Active Active Active Power
Ordering Information
Speed (ns) 25 45 Ordering Code CY14E256LA-SZ25XIT CY14E256LA-SZ25XI CY14E256LA-SZ45XIT CY14E256LA-SZ45XI
All the mentioned parts are Pb-free.
Package Diagram 51-85127
Package Type 32-pin SOIC
Operating Range Industrial
Ordering Code Definition
CY 14 E 256 L A-ZS 25 X I T Option: T - Tape and Reel Blank - Std. Pb-Free Package: ZS - 44 TSOP II SZ - 32 SOIC Data Bus: L - x8
Temperature: I - Industrial (-40 to 85 oC) Speed: 25 to 25 ns 45 to 45 ns
Die revision: Blank - No rev A - 1st Rev
Voltage: E - 5.0 V
Density: 256 - 256 Kb
14 - nvSRAM Cypress
Document Number: 001-54952 Rev. *F
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CY14E256LA
Package Diagrams
M
Figure 13. 44-Pin TSOP II (51-85087)
51-85087 *C
Figure 14. 32-Pin SOIC (51-85127)
PIN 1 ID
16 1
0.292[7.416] 0.299[7.594] 0.405[10.287] 0.419[10.642]
DIMENSIONS IN INCHES[MM] REFERENCE JEDEC MO-119
MIN. MAX.
17
32
PART # S32.3 STANDARD PKG. SZ32.3 LEAD FREE PKG.
SEATING PLANE
0.810[20.574] 0.822[20.878]
0.090[2.286] 0.100[2.540] 0.004[0.101] 0.050[1.270] TYP. 0.014[0.355] 0.020[0.508] 0.026[0.660] 0.032[0.812] 0.021[0.533] 0.041[1.041] 0.006[0.152] 0.012[0.304]
0.004[0.101] 0.0100[0.254]
51-85127 *B
Document Number: 001-54952 Rev. *F
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CY14E256LA
Acronyms
Acronyms Used
Acronym CMOS EIA I/O JEDEC nvSRAM RoHS RWI SOIC TSOP II Description complementary metal oxide semiconductor electronic industries alliance input/output joint electron devices engineering council nonvolatile static random access memory restriction of hazardous substances read and write inhibited small-outline integrated circuit thin small outline package
Document Conventions
Units of Measure
Symbol Kbit C K MHz A f s mA ms ns pF ps V W 1024 bits degrees celsius kilo ohms megahertz microamperes microfarads microseconds milliampere millisecond nanoseconds ohms picofarads picoseconds volts watts Unit of Measure
Document Number: 001-54952 Rev. *F
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Document History Page
Document Title: CY14E256LA 256-Kbit (32 K x 8) Nonvolatile SRAM Document Number: 001-54952 Revision ** *A *B *C *D ECN 2748216 2772059 2829117 2891356 2922858 Orig. of Change GVCH/PYRS GVCH GVCH GVCH GVCH Submission Date 08/04/09 09/30/09 12/16/09 03/12/10 04/26/10 New Datasheet Updated Software STORE, RECALL and Autostore Enable, Disable soft sequence Updated STORE cycles to QuantumTrap from 200K to 1 Million Added Contents. Moved to external web. Removed inactive parts from Ordering Information table. Updated links in Sales, Solutions, and Legal Information. Table 1: Added more clarity on HSB pin operation Hardware STORE Operation: Added more clarity on HSB pin operation Updated HSB pin operation in Figure 8 and updated footnote 21 Updated package diagram 51-85087 Change: ISB and ICC4 max value from 5 mA to 8 mA. Areas affected: DC Electrical Characteristics on page 8. Change: Template and styles update. Areas affected: Entire datasheet Fixed typo in Figure 8. Description of Change
*E
3030490
GVCH
09/15/10
*F
3143330
GVCH
01/17/2011
Document Number: 001-54952 Rev. *F
Page 18 of 19
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CY14E256LA
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
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PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
(c) Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-54952 Rev. *F
Revised January 17, 2011
Page 19 of 19
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